Active-matrix liquid crystal display devices that include a plurality of source bus lines (image signal lines) and a plurality of gate bus lines (scanning signal lines) are a conventionally well-known technology. In past implementations of this type of liquid crystal display device, a gate driver (scanning signal line driver circuit) for driving the gate bus lines was often packaged as an integrated circuit (IC) chip that was then mounted on the periphery of a substrate included in the liquid crystal panel. In recent years, however, it has gradually become more common to form the gate driver directly on a TFT substrate, which is one of the two glass substrates included in the liquid crystal panel. Such gate drivers are known as “monolithic” gate drivers, for example.
The display unit of an active-matrix liquid crystal display device includes a plurality of source bus lines, a plurality of gate bus lines, and a plurality of pixel formation regions that are respectively formed at the intersections between the source bus lines and the gate bus lines. These pixel formation regions are arranged in a matrix pattern to form a pixel array. Each pixel formation region includes a thin-film transistor (a switching element) in which the gate terminal is connected to the gate bus line that passes through the corresponding intersection and the source terminal is connected to the source bus line that passes through the corresponding intersection, a pixel capacitor for maintaining the pixel voltage, and the like. Such active-matrix liquid crystal display devices also include a gate driver of the type described above as well as a source driver (image signal line driver circuit) for driving the source bus lines.
Image signals that represent pixel voltages are transmitted via the source bus lines. However, the source bus lines cannot simultaneously transmit several rows worth of the image signals that represent pixel voltages. As a result, the image signals (charges) must be sequentially written, row by row, to the pixel capacitors in the pixel formation regions that are arranged in a matrix pattern. Therefore, the gate driver is implemented as a multistage shift register so that the gate bus lines can be sequentially selected each prescribed interval of time. Moreover, the stages of the shift register sequentially output active scanning signals in order to sequentially write the image signals to the pixel capacitors one row at a time, as described above. Note that in the present specification, the circuits that form the stages of the shift register will be referred to as “stage circuits.”
FIG. 38 is a circuit diagram of the most basic conventional configuration of a stage circuit. This stage circuit includes four thin-film transistors T81 to T84 and a single capacitor CAP. The stage circuit also includes an input terminal for a low-level DC supply voltage VSS, an output terminal 80, and four input terminals 81 to 84. The gate terminal of the thin-film transistor T81, the source terminal of the thin-film transistor T83, and the drain terminal of the thin-film transistor T84 are all connected together. As will be described below, the voltage of the region in which these terminals are connected to one another controls the state of the thin-film transistor T81 (that is, the ON and OFF states). In this way, the output of the stage circuit can be controlled. This region will therefore be referred to as the “output control node” below. The output control node is indicated by the reference character netA. Note that although typically whichever of the drain or source has the higher electric potential is referred to as the “drain,” in the present specification one side is simply defined to be the drain side and the other side to be the source side. Accordingly, the source voltage may potentially be greater than the drain voltage. Furthermore, for convenience, the magnitude of the low-level DC supply voltage VSS will be referred to simply as the “VSS voltage.”
The output terminal 80 outputs a scanning signal GOUT to be applied to the gate bus line that is connected to the stage circuit. A first gate clock signal CKA is input to the input terminal 81. A second gate clock signal CKB is input to the input terminal 82. Here, the phases of the first gate clock signal CKA and the second gate clock signal CKB are shifted from one another by 180°. A scanning signal that is output from the stage circuit of the previous stage is input to the input terminal 83 as a set signal S. A scanning signal that is output from the stage circuit of the next stage is input to the input terminal 84 as a reset signal R. Note that in the following description, the stage circuit of the previous stage will sometimes be referred to simply as “the previous stage,” and the stage circuit of the next stage will sometimes be referred to simply as “the next stage.”
In the thin-film transistor T81, the gate terminal is connected to the output control node netA, the drain terminal is connected to the input terminal 81, and the source terminal is connected to the output terminal 80. In the thin-film transistor T82, the gate terminal is connected to the input terminal 82, the drain terminal is connected to the output terminal 80, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T83, the gate terminal and the drain terminal are both connected to the input terminal 83 (that is, are diode-connected), and the source terminal is connected to the output control node netA. In the thin-film transistor T84, the gate terminal is connected to the input terminal 84, the drain terminal is connected to the output control node netA, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the capacitor CAP, one terminal is connected to the output control node netA, and the other terminal is connected to the output terminal 80.
Next, the operation of the stage circuit configured as illustrated in FIG. 38 will be described with reference to FIG. 39. Note that here, the period of time during which each stage circuit writes (charges) the pixel capacitor in the pixel formation region that is connected the corresponding gate bus line will be referred to as the “write operation period.” Moreover, periods of time other than the write operation period will be referred to as “normal operation periods.” In FIG. 39, the period from time t90 to time t92 corresponds to the write operation period, and the period prior to time t90 as well as the period after time t92 correspond to normal operation periods.
First, the operation of the stage circuit during the write operation period will be described. At time t90, a pulse in the set signal S is input to the input terminal 83. As illustrated in FIG. 38, the gate and drain terminals of the thin-film transistor T83 are diode-connected, and therefore the pulse in the set signal S sets the thin-film transistor T83 to the ON state, thereby charging the capacitor CAP. This causes the voltage of the output control node netA to increase, thereby setting the thin-film transistor T81 to the ON state. During the period from time t90 to t91, the first gate clock signal CKA is at the low level. Therefore, during this period of time, the scanning signal GOUT is maintained at the low level. Moreover, during the period from time t90 to t91, the reset signal R is also at the low level, and therefore the thin-film transistor T84 remains in the OFF state. As a result, the voltage of the output control node netA never decreases during this period of time.
At time t91, the first gate clock signal CKA switches from the low level to the high level. Because the thin-film transistor T81 is in the ON state at this time, as the voltage of the input terminal 81 increases, the voltage of the output terminal 80 also increases. Here, as illustrated in FIG. 38, the capacitor CAP is connected between the output control node netA and the output terminal 80, and therefore the increase in the voltage of the output terminal 80 causes an increase in the voltage of the output control node netA as well (the output control node netA is bootstrapped). As a result, a large voltage is applied to the gate terminal of the thin-film transistor T81, and the voltage of the scanning signal GOUT (that is, the voltage of the output terminal 80) increases to the high-level voltage of the first gate clock signal CKA. Due to this, the gate bus line that is connected to the output terminal 80 of the stage circuit enters the selected state. Moreover, during the period from time t91 to t92, the second gate clock signal CKB is at the low level. As a result, during this period, the thin-film transistor T82 remains in the OFF state, and the voltage of the scanning signal GOUT never decreases.
At time t92, the first gate clock signal CKA switches from the high level to the low level. Therefore, the voltage of the input terminal 81 decreases, the voltage of the output terminal 80 decreases, and the voltage of the output control node netA that is connected via the capacitor CAP decreases as well. Moreover, at time t92, a pulse in the reset signal R is input to the input terminal 84. This sets the thin-film transistor T84 to the ON state. As a result, the voltage of the output control node netA switches from the high level to the low level. Furthermore, at time t92, the second gate clock signal CKB switches from the low level to the high level. This sets the thin-film transistor T82 to the ON state. As a result, the voltage of the scanning signal GOUT decreases to the low level.
As described above, an active scanning signal GOUT is applied to the gate bus line corresponding to this stage circuit during the latter half of the write operation period. The scanning signal GOUT output from the stage circuit in a given stage is input to the next stage as the set signal S. In this way, the gate bus lines in the liquid crystal display device are sequentially selected, and DATa is written to the pixel capacitors one row at a time.
However, in the configuration described above, any noise that occurs due to the clock signal (that is, due to the first gate clock signal CKA) during the normal operation period can potentially cause fluctuations in the voltage of the scanning signal GOUT, which is supposed to be fixed at the low level during this period. Next, this problem will be described in more detail. Parasitic capacitance is formed between the electrodes of the thin-film transistors in the stage circuits included in shift registers. Accordingly, in the configuration illustrated in FIG. 38 as well, parasitic capacitance is formed between the gate and drain and between the gate and source of the thin-film transistor T81. As a result, when the first gate clock signal CKA switches from the low level to the high level, the gate voltage of the thin-film transistor T81 also increases due to this parasitic capacitance. In other words, the voltage of the output control node netA increases slightly (that is, the voltage of the output control node netA floats) despite being supposed to remain fixed at the low level. This causes a leakage current to flow through the thin-film transistor T81, thereby causing the voltage of the scanning signal GOUT to fluctuate. As illustrated in FIG. 39, the first gate clock signal CKA alternates between the low level and the high level at a prescribed cycle while the liquid crystal display device is operating. Therefore, the voltage of the scanning signal GOUT fluctuates at a prescribed cycle during the normal operation period. This can potentially cause abnormal operation and increased power consumption.
Therefore, stage circuits also typically include a circuit for maintaining the voltage of the output control node netA at the low level during normal operation periods (hereinafter, an “output control node stabilizer”) as well as a circuit (hereinafter, a “stabilization node controller”) for controlling the output control node stabilizer by controlling the voltage levels of nodes that are connected to the output control node stabilizer (hereinafter, “stabilization nodes,” and denoted by the reference character netB). FIG. 40 schematically illustrates a configuration of a stage circuit that includes an output control node stabilizer and a stabilization node controller. As illustrated in FIG. 40, this stage circuit includes a buffer 910, a scanning signal stabilizer 920, an output control node setter 930, an output control node resetter 940, an output control node stabilizer 950, and a stabilization node controller 960. Note that the thin-film transistor T81, the thin-film transistor T82, the thin-film transistor T83, and the thin-film transistor T84 in FIG. 38 respectively correspond to the buffer 910, the scanning signal stabilizer 920, the output control node setter 930, and the output control node resetter 940 in FIG. 40.
A specific example of a conventional stage circuit configuration that includes the output control node stabilizer 950 and the stabilization node controller 960 is disclosed in WO 2010/067641 Pamphlet, for example. FIG. 41 is a circuit diagram illustrating the configuration of the stage circuit disclosed in WO 2010/067641 Pamphlet. The stage circuit illustrated in FIG. 41 includes ten thin-film transistors T91 to T100 and a single capacitor CAP. This stage circuit also includes an output terminal 90 and six input terminals 91 to 96. The gate terminal of the thin-film transistor T91, the drain terminal of the thin-film transistor T92, the source terminal of the thin-film transistor T95, the gate terminal of the thin-film transistor T96, and the drain terminal of the thin-film transistor T97 are all connected together via an output control node netA. Moreover, the gate terminal of the thin-film transistor T92, the source terminal of the thin-film transistor T93, the drain terminal of the thin-film transistor T94, the drain terminal of the thin-film transistor T96, and the gate terminal of the thin-film transistor T100 are all connected together via a stabilization node netB.
In the thin-film transistor T91, the gate terminal is connected to the output control node netA, the drain terminal is connected to the input terminal 91, and the source terminal is connected to the output terminal 90. In the thin-film transistor T92, the gate terminal is connected to the stabilization node netB, the drain terminal is connected to the output control node netA, and the source terminal is connected to an input terminal for a DC supply voltage VSS. In the thin-film transistor T93, the gate terminal and the drain terminal are both connected to the input terminal 93 (that is, are diode-connected), and the source terminal is connected to the stabilization node netB. In the thin-film transistor T94, the gate terminal is connected to the input terminal 94, the drain terminal is connected to the stabilization node netB, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T95, the gate terminal and the drain terminal are both connected to the input terminal 95 (that is, are diode-connected), and the source terminal is connected to the output control node netA. In the thin-film transistor T96, the gate terminal is connected to the output control node netA, the drain terminal is connected to the stabilization node netB, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T97, the gate terminal is connected to the input terminal 96, the drain terminal is connected to the output control node netA, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T98, the gate terminal is connected to the input terminal 96, the drain terminal is connected to the output terminal 90, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T99, the gate terminal is connected to the input terminal 92, the drain terminal is connected to the output terminal 90, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the thin-film transistor T100, the gate terminal is connected to the stabilization node netB, the drain terminal is connected to the output terminal 90, and the source terminal is connected to the input terminal for the DC supply voltage VSS. In the capacitor CAP, one terminal is connected to the output control node netA, and the other terminal is connected to the output terminal 90.
Note that in the configuration illustrated in FIG. 41, the thin-film transistor T92 constitutes the output control node stabilizer 950, and the thin-film transistor T93, the thin-film transistor T94, and the thin-film transistor T96 constitute the stabilization node controller 960.
FIG. 42 is a timing chart for explaining the operation of the stage circuit configured as illustrated in FIG. 41. As illustrated in FIG. 42, this stage circuit operates using a four-phase clock signal (which includes a first gate clock signal CKA, a second gate clock signal CKB, a third gate clock signal CKC, and a fourth gate clock signal CKD) in which the phases are each shifted by 90°. Next, the normal operation periods in FIG. 42 will be described. During the normal operation periods, the voltage of the output control node netA is maintained at the low level, and therefore the thin-film transistor T96 remains in the OFF state. Moreover, when the third gate clock signal CKC is at the high level and the fourth gate clock signal CKD is at the low level, the thin-film transistor T93 takes the ON state and the thin-film transistor T94 takes the OFF state. Conversely, when the third gate clock signal CKC is at the low level and the fourth gate clock signal CKD is at the high level, the thin-film transistor T93 takes the OFF state and the thin-film transistor T94 takes the ON state. In this way, as illustrated in FIG. 42, the voltage of the stabilization node netB is set to the high level at prescribed time intervals during the normal operation periods. Therefore, during the normal operation periods, the thin-film transistor T92 is set to the ON state and the voltage of the output control node netA is set to the VSS voltage at prescribed time intervals. This prevents the voltage of the output control node netA from floating during the normal operation periods, thereby making it possible to provide a monolithic gate driver that does not exhibit any abnormal operation. Moreover, the thin-film transistor T96 is provided to prevent the voltage of the stabilization node netB from being set to the high level during the write operation period.